Technical Field
The present disclosure generally relates to various geometries for gate-all-around transistor devices built on a semiconductor substrate and, in particular, to vertically oriented gate-all-around transistors in which current flows in a direction transverse to the surface of the semiconductor substrate.
Description of the Related Art
A gate-all-around FET, or GAA FET, is a non-planar metal-oxide-semiconductor (MOS) transistor design in which the gate fully wraps around the conducting channel for maximum control of current flow therein. In the GAA FET, the channel is configured as a cylindrical nanowire that is surrounded by a gate oxide. The gate then surrounds the gate oxide.
Source and drain regions are positioned on either end of the channel. Some existing GAA FETs are horizontal GAA FETs, oriented such that the nanowire extends in a horizontal direction that is substantially parallel to the surface of the semiconductor substrate. Such horizontal GAA FETs are described in, for example, U.S. Patent Application Publication No. 2013/0341596 to Chang et al., of IBM, and in U.S. Patent Publication No. 2015/0372104, to Liu et al., of STMicroelectronics.
Vertical GAA FET structures have also been developed in which a current-carrying nanowire is oriented substantially perpendicular to a top surface of a silicon substrate. The nanowire is grown epitaxially and doped appropriately to form source, channel, and drain regions in a stacked arrangement. The vertical GAA FET is intended to meet design and performance criteria for integrated circuits of the 7 nm technology generation. Such devices are described in U.S. patent application Ser. Nos. 14/588,337 and 14/675,536 assigned to the same assignee as the present patent application.
One particular challenging aspect of the vertical GAA FET stacked design is the interconnect structure. In particular, making electrical contact to the lowest terminal of the vertical GAA FET, i.e., the source or the drain, can be awkward because the lower terminal is not accessible from the top side of the semiconductor substrate, once the vertical GAA FET is formed. In previous designs, some electrical contacts to the lower terminals of GAA FETs were made via the back side of the substrate.